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1 document # sram107 rev c. revisedjune 2008 p4c168/p4c168l , p4c169, p4c170 ultra high speed 4k x 4 s tatic cmos rams description the p4c168, p4c169 and p4c170 are a family of 16,384-bit ultra high-speed static rams organized as 4k x 4. all three devices have common input/output ports.the p4c168 enters the standby mode when the chip enable (ce) control goes high; with cmos input levels, power consumption is only 83mw in this mode. both the p4c169 and the p4c170 offer a fast chip select access time that is only 67% of the address access time. in addition, the p4c170 includes an output enable (oe) control to eliminate data bus contention. the rams oper - ate from a single 5v 10% tolerance power supply. features full cmos, 6t cell high speed (equal access and cycle times) C 12/15/20/25/35ns (commercial) C 20/25/35/45/55/70ns (p4c168 military) low power operation (commercial) C 715 mw active C 193 mw standby (ttl input) p4c168 C 83 mw standby (cmos input) p4c168 single 5v10% power supply fully ttl compatible, common i/o ports three options C p4c168 low power standby mode C p4c169 fast chip select control C p4c170 fast chip select, output enable controls standard pinout (jedec approved) C p4c168: 20-pin dip, soj, lcc, soic, cerpack, and flat pack C p4c169: 20-pin dip and soic C p4c170: 22-pin dip access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is used to reduce power consumption to a low 715 mw active, 193 mw standby. the p4c168 and p4c169 are available in 20-pin (p4c170 in 22-pin) 300 mil dip packages providing excellent board level densities. the p4c168 is also available in 20-pin 300 mil soic, soj, cerpack, and flat pack packages. the p4c169 is also available in a 20-pin 300 mil soic package. pin c onfigurations functional block diagram p4c168 p4c169 dip (p2, c6, d 2) dip (p2) soic (s2) soic (s2) soj (j2) cerpack (f2) solder seal flat pack (fs-2) p4c170 dip (p3)
p4c168/p4c168l, p4c169, p4c170 page 2 of 14 document # sram107 rev c recommended operating conditions capacitances (2) (v cc = 5.0v, t a = 25c, f = 1.0mhz) dc electrical characteristics maximum r atings (1) grade (2) ambient temp gnd v cc commercial 0c to 70c 0v 5.0v 10% military -55c to +125c 0v 5.0v 10% symbol parameter value unit v cc power supply pin with respect to gnd -0.5 to +7 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 to v cc + 0.5 v t a operating temperature -55 to +125 c symbol parameter value unit t bias temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma sym parameter conditions typ. unit c in input capacitance v in =0v 5 pf c out output capacitance v out =0v 7 pf sym parameter test conditions p4c168/169/170 p4c168l unit min max min max v ih input high voltage 2.2 v cc +0.5 2.2 v cc +0.5 v v il input low voltage -0.5 (3) 0.8 -0.5 (3) 0.8 v v hc cmos input high voltage v cc -0.2 v cc +0.5 v cc -0.2 v cc +0.5 v v lc cmos input low voltagte -0.5 (3) 0.2 -0.5 (3) 0.2 v v cd input clamp diode voltage v cc =min, i in =-18 ma -1.2 -1.2 v v ol output low voltage (ttl load) i ol =+8 ma, v cc =min 0.4 0.4 v v olc output load voltage (cmos load) i olc =+100a, vcc=min. 0.2 0.2 v v oh output high voltage (ttl load) i oh =-4 ma, v cc =min 2.4 2.4 v v ohc output high voltage (cmos load) i ohc =-100 a, v cc =min v cc -0.2 v cc -0.2 v i li input leakage current (military) v cc =max, v in =gnd to v cc -10 +10 -5 +5 a input leakage current (commercial) -5 +5 -2 +2 i lo output leakage current (military) v cc =max, cs =v ih , v out =gnd to v cc -10 +10 -5 +5 a output leakage current (commer - cial) -5 +5 -2 +2 i cc dynamic operating current (military) v cc =max,f=max, outputs open 120 120 ma dynamic operating current (com - mercial) 100 100 i sb standby power supply current (ttl input levels) (military) ce 1 v ih ,v cc =max,f=max,outputs open 40 40 ma standby power supply current (ttl input levels) (commercial) 35 35 i sb1 standby power supply current (cmos input levels) (military) ce 1 v hc ,v cc =max,f=0,outputs open,v in v lc or v in v hc 20 1 ma standby power supply current (cmos input levels) (commercial) 15 0.2 notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability.. 2. this parameter is sampled and not 100% tested. 3. transient inputs with v il and i il not more negative than -3.0v and -100ma, respectively, are permissible for pulse widths up to 20 ns.
p4c168/p4c168l, p4c169, p4c170 page 3 of 14 document # sram107 rev c ac characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (4) sym parameter -12 -15 -20 -25 -35 unit min max min max min max min max min max t rc read cycle time 12 15 20 25 35 ns t aa address access time 12 15 20 25 35 ns t ac chip enable access time 12 15 20 25 35 ns t ac ? chip select access time 8 9 12 15 20 ns t oh output hold from address change 2 2 2 2 2 ns t lz ? chip enable to output in low z 2 2 2 2 2 ns t hz ? chip disable to output in high z 7 8 9 10 15 ns t oe ? output enable to data valid 8 10 12 15 15 ns t olz ? output enable to output in low z 0 0 0 0 0 ns t ohz ? output disable to output in high z 6 7 9 11 15 ns t rcs read command setup time 0 0 0 0 0 ns t rch read command hold time 0 0 0 0 0 ns t pu chip enable to power up time 0 0 0 0 0 ns t pd chip disable to power down time 12 15 20 25 35 ns sym parameter test condition min typ. * v cc = max v cc = 2.0v 3.0v 2.0v 3.0v unit v dr v cc for data retention 2.0 v i ccdr data retention current (military) ce v cc - 0.2v, v in v cc - 0.2v, or v in 0.2v 2 3 200 300 a data retention current (commercial) 0.5 1.0 20 30 a t cdr chip deselect to data retention time 0 ns t r ? operation recovery time t rc ns data retention characteristics (p4c168l only ) data retention waveform notes: 4. extended temperature operation guaranteed with 400 linear feet per minute of air fow.
p4c168/p4c168l, p4c169, p4c170 page 4 of 14 document # sram107 rev c timing w aveform of read cycle no. 1 (address controlled) (5,6) notes: 5. we is high for read cycle. 6. ce / cs and oe are low for read cycle. p4c168 only ? p4c170 only ? chip select/deselect for p4c169 and p4c170 ac characteristicsread cycle (continued) (v cc = 5v 10%, all temperature ranges) (2) sym parameter -45 -55 -70 unit min max min max min max t rc read cycle time 45 55 70 ns t aa address access time 45 55 70 ns t ac chip enable access time 45 55 70 ns t ac ? chip select access time 25 30 35 ns t oh output hold from address change 2 2 2 ns t lz ? chip enable to output in low z 2 2 2 ns t hz ? chip disable to output in high z 25 25 30 ns t oe ? output enable to data valid 20 25 30 ns t olz ? output enable to output in low z 0 0 0 ns t ohz ? output disable to output in high z 20 25 30 ns t rcs read command setup time 0 0 0 ns t rch read command hold time 0 0 0 ns t pu chip enable to power up time 0 0 0 ns t pd chip disable to power down time 45 55 70 ns
p4c168/p4c168l, p4c169, p4c170 page 5 of 14 document # sram107 rev c notes: 7. address must be valid prior to, or coincident with ce / cs transition low. for fast cs , t aa must still be met. 8. transition is measured 200mv from steady state voltage prior to change, with loading as specifed in figure 1. 9. read cycle time is measured from the last valid address to the frst transitioning address. timing w aveform of read cycle no. 2 ( ce / cs controlled) (5,7) timing w aveform of read cycle no. 3p4c170 o nly ( oe controlled) (5)
p4c168/p4c168l, p4c169, p4c170 page 6 of 14 document # sram107 rev c ac electrical characteristics - write cycle (v cc = 5v 10%, all temperature ranges) (2) ac electrical characteristics - write cycle (continued) (v cc = 5v 10%, all temperature ranges) (2) sym parameter -12 -15 -20 -25 -35 unit min max min max min max min max min max t wc write cycle time 12 15 18 20 30 ns t cw chip enable time to end of write 12 15 18 20 30 ns t aw address valid to end of write 12 15 18 20 30 ns t as address setup time 0 0 0 0 0 ns t wp write pulse width 12 15 18 20 30 ns t ah address hold time 0 0 0 0 0 ns t dw data valid to end of write 7 8 10 10 15 ns t dh data hold time 0 0 0 0 0 ns t wz write enable to output in high z 4 5 6 7 13 ns t ow output active from end of write 0 0 0 0 0 ns sym parameter -45 -55 -70 unit min max min max min max t wc write cycle time 45 55 70 ns t cw chip enable time to end of write 40 50 60 ns t aw address valid to end of write 40 50 60 ns t as address setup time 0 0 0 ns t wp write pulse width 40 50 60 ns t ah address hold time 0 0 0 ns t dw data valid to end of write 20 20 25 ns t dh data hold time 3 3 3 ns t wz write enable to output in high z 20 25 30 ns t ow output active from end of write 0 0 0 ns
p4c168/p4c168l, p4c169, p4c170 page 7 of 14 document # sram107 rev c timing w aveform of write cycle no. 2 ( ce / cs controlled) (10) truth t ables p4c168 (p4c169) p4c170 notes: 10. ce / cs and we must be low for write cycle. 11. if ce / cs goes high simultaneously with we high, the output remains in a high impedance state. 12. write cycle time is measured from the last valid address to the frst transitioning address. timing w aveform of write cycle no. 1 ( we controlled) (10) mode ce ( cs ) we output standby (deselect) h x high z read l h d out write l l high z mode ce we oe output deselect h x x high z read l h l d out output inhibit l h h high z write l l x high z
p4c168/p4c168l, p4c169, p4c170 page 8 of 14 document # sram107 rev c * including scope and test fxture. note: because of the ultra-high speed of the p4c168, p4c169 and p4c170 care must be taken when testing these devices; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a high frequency capacitor of 0.01 f is also required between v cc figure 1. output load figure 2. thevenin equivalent ac test conditions and ground. to avoid signal refections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). lcc pin configuration lcc (l9) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2
p4c168/p4c168l, p4c169, p4c170 page 9 of 14 document # sram107 rev c ordering i nformation selection guide the p4c168/p4c168l, p4c169 and p4c170 are available in the following temperature, speed and package options. ? p4c168 and p4c169 only. ?? p4c168 * military temperature range with mil-std-883, class b processing. n/a = not available temperature range package speed 12 15 20 25 35 45 55 70 commercial temperature plastic dip -12pc -15pc -20pc -25pc n/a n/a n/a n/a plastic soic? -12sc -15sc -20sc -25sc n/a n/a n/a n/a plastic soj?? -12jc -15jc -20jc -25jc n/a n/a n/a n/a military tem - perature (p4c168 only) lcc n/a -15lm -20lm -25lm -35lm -45lm -55lm -70lm cerdip n/a -15dm -20dm -25dm -35dm -45dm -55dm -70dm side brazed dip n/a -15cm -20cm -25cm -35cm -45cm -55cm -70cm cerpack n/a -15fm -20fm -25fm -35fm -45fm -55fm -70fm solder seal flat pack n/a -15fsm -20fsm -25fsm -35fsm -45fm -55fm -70fm military pro - cessed* (p4c168 only) lcc n/a -15lmb -20lmb -25lmb -35lmb -45lmb -55lmb -70lmb cerdip n/a -15dmb -20dmb -25dmb -35dmb -45dmb -55dmb -70dmb side brazed dip n/a -15cmb -20cmb -25cmb -35cmb -45cmb -55cmb -70cmb cerpack n/a -15fmb -20fmb -25fmb -35fmb -45fmb -55fmb -70fmb solder seal flat pack n/a -15fsmb -20fsmb -25fsmb -35fsmb -45fsmb -55fsmb -70fsmb
p4c168/p4c168l, p4c169, p4c170 page 10 of 14 document # sram107 rev c pkg # j2 # pins 20 (300 mil) symbol min max a 0.120 0.140 a1 0.080 - b 0.014 0.020 c 0.008 0.013 d 0.496 0.512 e 0.050 bsc e 0.335 0.347 e1 0.292 0.300 e2 0.267 bsc q 0.025 - soj small outline ic package solder seal flat package pkg # fs-2 # pins 20 symbol min max a 0.045 0.115 b 0.015 0.022 b1 0.015 0.019 c 0.004 0.009 c1 0.004 0.006 d - 0.540 e 0.245 0.300 e1 - 0.330 e2 0.130 - e3 0.030 - e 0.050 bsc k 0.008 0.015 l 0.250 0.370 q 0.026 0.045 s1 0.000 - m - 0.002 n 20
p4c168/p4c168l, p4c169, p4c170 page 11 of 14 document # sram107 rev c pkg # l9 # pins 20 symbol min max a 0.060 0.075 a1 0.050 0.066 b1 0.022 0.028 d 0.280 0.305 d1 0.150 bsc d2 0.075 bsc d3 - 0.305 e 0.420 0.440 e1 0.250 bsc e2 0.125 bsc e3 - 0.440 e 0.050 bsc h 0.020 ref j 0.010 ref l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.098 nd 4 ne 6 rectangular leadless chip carrier pkg # p2 # pins 20 (300 mil) symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 0.980 1.060 e1 0.240 0.280 e 0.300 0.325 e 0.100 bsc eb - 0.430 l 0.115 0.150 0 15 plastic dual in-line package (p4c168, p4c169)
p4c168/p4c168l, p4c169, p4c170 page 12 of 14 document # sram107 rev c pkg # s2 # pins 20 (300 mil) symbol min max a 0.093 0.104 a1 0.004 0.012 b2 0.013 0.020 c 0.009 0.012 d 0.496 0.511 e 0.050 bsc e 0.291 0.299 h 0.394 0.419 h 0.010 0.029 l 0.016 0.050 0 8 soic/sop small outline ic package pkg # p3 # pins 22 (300 mil) symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 1.145 1.165 e1 0.240 0.280 e 0.300 0.325 e 0.100 bsc eb - 0.430 l 0.115 0.150 0 15 plastic dual in-line package (p4c170)
p4c168/p4c168l, p4c169, p4c170 page 13 of 14 document # sram107 rev c cerdip dual in-line package pkg # d2 # pins 20 (300 mil) symbol min max a - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.060 e 0.220 0.310 ea 0.300 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.070 s1 0.005 - 0 15
p4c168/p4c168l, p4c169, p4c170 page 14 of 14 document # sram107 rev c revisions document number sram 107 document title p4c168, p4c169, p4c170 ultra high speed 4k x 4 static cmos rams rev issue date originator description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid b may-08 jdb added p4c168l, updated document formatting c jun-08 jdb corrected order info drawing

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